1. Field of the Invention
The present invention relates to a method of forming a contact hole in a semiconductor device.
2. Discussion of the Related Art
Generally, to keep up with rapid developments in information media such as a computer and the like, semiconductor fabrication methods have been remarkably developed. For semiconductor devices, further enhancement in the degree of integration, nano-sized implementations, operational speeds, and the like, are needed. As known by Moore's Law, the degree of integration of semiconductor devices is biannually raised twice higher. Inevitably, new problems which were never taken into consideration arise due to the reduced chip size and the reduced critical dimension (CD).
Meanwhile, a premetal dielectric (PMD) layer, which is an insulating interlayer for isolating a polysilicon gate from a metal line, needs to be efficient in gap-fill performance, gathering performance, and planarization.
The phrase “gap-fill performance ” refers to a capability of filling up a step difference due to a pattern of a semiconductor device. And, the phrase “gathering performance ” refers to capability of trapping mobile ions degrading a device characteristic such as natrium ions and other metal ions.
A silicon oxide (SiO2) layer frequently used as an insulating layer is incapable of filling a step difference formed by a polysilicon gate. Since voids are formed in the PMD layer of silicon oxide, the PMD layer fails to be dense or thick to degrade the device characteristic. Moreover, a conductor material is formed in the voids on depositing the conductor material as a contact plug, whereby the PMD layer of silicon oxide lowers a production yield of the semiconductor device.
To overcome such a problem, silicon oxide is replaced by borophosphosilicate glass (BPSG) having excellent gap-fill performance as a PMD layer. A BPSG layer is generally formed in a manner of introducing boron (B) and phosphor (P) into a reaction chamber together with silicon and oxygen source for forming silicon oxide. In doing so, boron is a dopant for improving the gap-fill performance and phosphor is a dopant for improving the gather performance of mobile ions.
FIG. 1 is a cross-sectional diagram of a contact hole in a semiconductor device according to a related art.
Referring to FIG. 1, shallow trench isolation (STI) is carried out on a semiconductor substrate 100 to form a device isolation layer 102. Subsequently, a gate oxide layer 104, a polysilicon gate 106, source/drain (not shown in the drawing), a sidewall nitride layer 108, a silicide layer 110, and the like are formed on the semiconductor substrate 100. And, a PMD liner layer 112, a BPSG layer 114, and an oxide layer 116 are sequentially stacked over the substrate including the silicide layer 110.
Thereafter, contact holes for electric connection to the source/drain are formed on the semiconductor substrate 100 in a following manner. First of all, a dry etch is carried out on the semiconductor substrate 100 to form the contact holes exposing the silicide layer 110 onto the source/drain. After completion of the dry etch, wet cleaning is carried out on the semiconductor substrate 100 to remove polymers generated from the dry etch and photoresist. Specifically, the wet cleaning includes sulfuric hydroxide (SH) cleaning at about 130° C. and new cleaning-2 (NC-2) at about 75° C.
However, in performing the wet cleaning, a portion 120 of the BPSG layer 114 is overetched to degrade device characteristics. And, in forming a contact plug to fill up the contact hole, a metal material of the contact plug intrudes the overetched portion 120 to short-circuit the semiconductor device.